1. Field of the Invention
The present invention relates to CMUTS and, more particularly, to a low frequency CMUT with thick oxide.
2. Description of the Related Art
A capacitive micromachined ultrasonic transducer (CMUT) is a semiconductor-based ultrasonic transducer that utilizes a change in capacitance to convert received ultrasonic waves into an electrical signal, and to convert an alternating electrical signal into transmitted ultrasonic waves.
FIGS. 1A-1B show views that illustrate an example of a prior-art CMUT 100. FIG. 1A shows a plan view of CMUT 100, while FIG. 1B shows a cross-sectional view taken along line 1B-1B of FIG. 1A. As shown in FIGS. 1A-1B, CMUT 100 includes a conventionally-formed semiconductor substrate 110, and a post oxide structure 112 that touches the top surface of semiconductor substrate 110. Post oxide structure 112, in turn, has substrate contact openings 114 that extend completely through post oxide structure 112 to expose semiconductor substrate 110.
As further shown in FIGS. 1A-1B, CMUT 100 includes a non-conductive structure 116 that touches the top surface of semiconductor substrate 110, and a conductive structure 120 that touches the top surface of post oxide structure 112 and lies over non-conductive structure 116 to form a vacuum-sealed cavity 122. In the present example, conductive structure 120 includes a semiconductor structure 124 such as, for example, single crystal silicon, and an overlying metal structure 126, such as an aluminum copper plate.
In addition, CMUT 100 includes substrate bond pads 130 that lie within the substrate contact openings 114 to make electrical connections to semiconductor substrate 110, and a passivation layer 132 that touches and lies over post oxide structure 112, conductive structure 120, and the substrate bond pads 130. Passivation layer 132 has substrate bond pad openings 134 that expose the substrate bond pads 130, and a conductor opening 136 that exposes a region of conductive structure 120 which functions as a bond pad. Further, CMUT 100 has an acoustic dampening structure 140 that touches the bottom surface of semiconductor substrate 110.
In operation, a first bias voltage V1 is placed on semiconductor substrate 110, which functions as a first capacitor plate, and a second bias voltage V2 is placed on conductive structure 120, which functions as second capacitor plate. Thus, the voltage across the capacitor plates lies across vacuum-sealed cavity 122. When used as a receiver, an ultrasonic wave causes conductive structure 120 to vibrate. The vibration varies the capacitance across the first and second capacitor plates, thereby generating an electrical signal that varies as the capacitance varies.
When used as a transmitter, an alternating electrical signal applied across the biased first and second capacitor plates causes conductive structure 120 to vibrate which, in turn, transmits ultrasonic waves. The rate or frequency at which conductive structure 120 vibrates depends on the volume of vacuum-sealed cavity 122, and the stiffness of conductive structure 120.
In addition to transmitting ultrasonic waves outward, ultrasonic waves are also transmitted backward towards the bottom surface of semiconductor substrate 110. These backward ultrasonic waves can resonate within semiconductor substrate 110 depending on the thickness of semiconductor substrate 110 and the frequency of operation, and can interfere with the quality of the resultant image. Acoustic dampening structure 140 absorbs and dampens the ultrasonic waves in semiconductor substrate 110.
FIGS. 2A-2B show views that illustrate an example of a prior-art CMUT array 200. FIG. 2A shows a plan view of array 200, while FIG. 2B shows a cross-sectional view taken along line 2B-2B of FIG. 2A. As shown in the FIGS. 2A-2B example, CMUT array 200 includes three CMUTS 100 in a single row.
FIGS. 3A-3N show cross-sectional views that illustrate an example of a prior-art method of forming a CMUT. As shown in FIG. 3A, the method utilizes a conventionally-formed single-crystal silicon wafer 310. Silicon wafer 310 has rows and columns of die-sized regions, and one or more CMUTS can be simultaneously formed in each die-sized region. For simplicity, FIGS. 3A-3N illustrate the formation of a single CMUT.
As further shown in FIG. 3A, the method begins by forming a post oxide structure 312 on the top surface of silicon wafer 310 using the well-known local oxidation of silicon (LOCOS) process. The LOCOS process also forms a backside oxide structure 314 that touches the bottom surface of silicon wafer 310 at the same time. Following this, as shown in FIG. 3B, a cell oxide layer 316 is grown on the exposed regions of the top surface of silicon wafer 310.
After cell oxide layer 316 has been formed, as shown in FIG. 3C, a silicon-on-oxide (SOI) wafer 320 is fusion bonded to the top surface of post oxide structure 312 to form a cavity 322. SOI wafer 320 has a handle wafer 324, an insulation layer 326 that touches handle wafer 324, and a single-crystal silicon substrate structure 328. Substrate structure 328, in turn, has a first surface that touches insulation layer 326, and a second surface that touches post oxide structure 312.
Cavity 322, in turn, has a depth that is measured vertically from the top surface of cell oxide layer 316 to the second surface of substrate structure 328. The thickness of cell oxide layer 316 defines the position of the top surface of cell oxide layer 316. In addition, the height of post oxide structure 312 over the top surface of silicon wafer 310 defines the position of the second surface of substrate structure 328.
The thickness of cell oxide layer 316 is relatively small compared to the height of post oxide structure 312 over the top surface of silicon wafer 310. As a result, the depth of cavity 322 is substantially defined by the height of post oxide structure 312 over the top surface of silicon wafer 310. In addition, substrate structure 328 of SOI wafer 320 is fusion bonded to the top surface of post oxide structure 312 of silicon wafer 310 in a vacuum to vacuum seal cavity 322.
After substrate structure 328 has been fusion bonded to post oxide structure 312, as shown in FIG. 3D, handle wafer 324 is removed in a conventional manner, followed by the conventional removal of insulation layer 326. Next, as shown in FIG. 3E, a patterned photoresist layer 330 is formed on the first surface of substrate structure 328. Once patterned photoresist layer 330 has been formed, as shown in FIG. 3F, the exposed region of substrate structure 328 is etched to form a CMUT membrane 332. Patterned photoresist layer 330 is then removed in a conventional manner.
As shown in FIG. 3G, after the removal of photoresist layer 330, a patterned photoresist layer 340 is formed on post oxide structure 312 and CMUT membrane 332. Once patterned photoresist layer 340 has been formed, as shown in FIG. 3H, the exposed regions of post oxide structure 312 are etched until silicon wafer 310 has been exposed. Patterned photoresist layer 340 is then removed in a conventional manner.
Following the removal of photoresist layer 340, as shown in FIG. 3I, a metal layer 342, such as a layer of aluminum copper, is deposited to touch silicon wafer 310, post oxide structure 312, and CMUT membrane 332. After this, a patterned photoresist layer 350 is formed on metal layer 342.
Next, as shown in FIG. 3J, the exposed region of metal layer 342 is etched to form semiconductor bond pads 352 that extend through post oxide structure 312 to touch silicon wafer 310, and a metal plate 354 that touches the top surface of CMUT membrane 332. Patterned photoresist layer 350 is then removed in a conventional manner.
As shown in FIG. 3K, after patterned photoresist layer 350 has been removed, a passivation layer 356 is formed to touch post oxide structure 312, CMUT membrane 332, the bond pads 352, and metal plate 354. Once passivation layer 356 has been formed, a patterned photoresist layer 360 is formed on passivation layer 356.
After this, as shown in FIG. 3L, the exposed regions of passivation layer 356 are etched to form openings that expose the semiconductor bond pads 352, and an opening, like opening 136 in FIG. 1A, that exposes a bond pad region of metal plate 354. As shown in FIG. 3M, patterned photoresist layer 360 is then removed in a conventional manner.
Next, the resulting structure is flipped over for processing, and backside oxide structure 314 is removed in a conventional manner. For example, backside oxide structure 314 can be removed using chemical mechanical polishing. Alternately, backside oxide structure 314 can be removed using a single-sided wet etch, such as a SEZ etch.
Following the removal of backside oxide structure 314, an acoustic damping structure 362, such as a tungsten epoxy mixture, is deposited onto the bottom side of silicon wafer 310 to form, as shown in FIG. 3N, a CMUT 364. Silicon wafer 310 is then diced to form a number of individual die that each has one or more CMUTS 364.
In the present example, cavity 322 has a depth of approximately 0.2 μm and a diameter of approximately 36.0 μm. In addition, CMUT membrane 332, metal plate 354, and the overlying region of passivation layer 356 vibrate at frequencies of approximately 10-20 MHz. These frequencies are suitable for contact or near contact body imaging applications, like echo cardiograms, but are not suitable for airborne ultrasound applications where, for example, the object to be detected, such as the hand motions of a person playing a game, is one or more meters away.
Instead, airborne ultrasound applications require much lower frequencies, such as 100-200 KHz. If CMUT 364 were scaled up in size to operate at these lower frequencies, then CMUT 364 would require a larger cell diameter (e.g. increasing from about 36 μm to about 1 mm-2 mm), a thicker CMUT membrane 332 (e.g. increasing from 2 μm to 5 μm-40 μm), and a deeper cell cavity 322 (e.g. increasing from 0.2 μm to fpm-12 μm). A deeper cell cavity is required to accommodate the atmospheric deflection of CMUT membrane 332, which can be on the order of several microns. For proper CMUT operation, CMUT membrane 332 should not touch the bottom surface of cavity 322, but rather be a fixed distance of one or more microns above the bottom surface of cavity 322.
Since the height of post oxide structure 312 substantially determines the depth of cavity 322, scaling up CMUT 364 requires that post oxide structure 312 have a height above the top surface of silicon wafer 310 of approximately fpm-12 μm, or a total thickness of 2 μm-24 μm. However, forming a post oxide structure with a thickness that exceeds approximately 5 μm (or heights that exceed 2.5 μm) is difficult to accomplish because the rate of oxide growth slows dramatically when the thickness of the post oxide structure approaches 5 μm.
As a result, it is difficult to scale up CMUT 364 to accommodate these lower frequencies. Thus, there is a need for an approach to forming low frequency CMUTS for airborne ultrasonic applications.